HelenOS sources
CONTROL_REG_GEN_WRITE 225 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CSSELR, c0, 2, c0, 0);
CONTROL_REG_GEN_WRITE 227 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(VPIDR, c0, 4, c0, 0);
CONTROL_REG_GEN_WRITE 229 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(VMPIDR, c0, 4, c0, 5);
CONTROL_REG_GEN_WRITE 261 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(SCTLR, c1, 0, c0, 0);
CONTROL_REG_GEN_WRITE 263 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ACTLR, c1, 0, c0, 1);
CONTROL_REG_GEN_WRITE 275 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CPACR, c1, 0, c0, 2);
CONTROL_REG_GEN_WRITE 291 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(SCR, c1, 0, c1, 0);
CONTROL_REG_GEN_WRITE 293 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(SDER, c1, 0, c1, 1);
CONTROL_REG_GEN_WRITE 303 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(NSACR, c1, 0, c1, 2);
CONTROL_REG_GEN_WRITE 307 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HSCTLR, c1, 4, c0, 0);
CONTROL_REG_GEN_WRITE 309 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HACTLR, c1, 4, c0, 1);
CONTROL_REG_GEN_WRITE 312 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HCR, c1, 4, c1, 0);
CONTROL_REG_GEN_WRITE 314 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HDCR, c1, 4, c1, 1);
CONTROL_REG_GEN_WRITE 316 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HCPTR, c1, 4, c1, 2);
CONTROL_REG_GEN_WRITE 318 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HSTR, c1, 4, c1, 3);
CONTROL_REG_GEN_WRITE 320 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HACR, c1, 4, c1, 7);
CONTROL_REG_GEN_WRITE 337 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0);
CONTROL_REG_GEN_WRITE 341 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TTBR1, c2, 0, c0, 1);
CONTROL_REG_GEN_WRITE 343 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TTBCR, c2, 0, c0, 2);
CONTROL_REG_GEN_WRITE 348 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HTCR, c2, 4, c0, 2);
CONTROL_REG_GEN_WRITE 350 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(VTCR, c2, 4, c1, 2);
CONTROL_REG_GEN_WRITE 354 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TTBR0H, c2, 0, c2, 0);
CONTROL_REG_GEN_WRITE 356 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TTBR1H, c2, 0, c2, 1);
CONTROL_REG_GEN_WRITE 358 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HTTBRH, c2, 0, c2, 4);
CONTROL_REG_GEN_WRITE 360 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(VTTBRH, c2, 0, c2, 6);
CONTROL_REG_GEN_WRITE 364 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DACR, c3, 0, c0, 0);
CONTROL_REG_GEN_WRITE 368 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DFSR, c5, 0, c0, 0);
CONTROL_REG_GEN_WRITE 370 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(IFSR, c5, 0, c0, 1);
CONTROL_REG_GEN_WRITE 373 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ADFSR, c5, 0, c1, 0);
CONTROL_REG_GEN_WRITE 375 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(AIFSR, c5, 0, c1, 1);
CONTROL_REG_GEN_WRITE 378 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HADFSR, c5, 4, c1, 0);
CONTROL_REG_GEN_WRITE 380 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HAIFSR, c5, 4, c1, 1);
CONTROL_REG_GEN_WRITE 382 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HSR, c5, 4, c2, 0);
CONTROL_REG_GEN_WRITE 385 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DFAR, c6, 0, c0, 0);
CONTROL_REG_GEN_WRITE 387 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(IFAR, c6, 0, c0, 2);
CONTROL_REG_GEN_WRITE 390 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HDFAR, c6, 4, c0, 0);
CONTROL_REG_GEN_WRITE 392 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HIFAR, c6, 4, c0, 2);
CONTROL_REG_GEN_WRITE 394 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HPFAR, c6, 4, c0, 4);
CONTROL_REG_GEN_WRITE 413 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CP15ISB, c7, 0, c5, 4);
CONTROL_REG_GEN_WRITE 414 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(BPIALL, c7, 0, c5, 6);
CONTROL_REG_GEN_WRITE 415 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(BPIMVA, c7, 0, c5, 7);
CONTROL_REG_GEN_WRITE 419 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCISW, c7, 0, c6, 2);
CONTROL_REG_GEN_WRITE 423 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCCSW, c7, 0, c10, 2);
CONTROL_REG_GEN_WRITE 426 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CP15DSB, c7, 0, c10, 4);
CONTROL_REG_GEN_WRITE 429 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CP15DMB, c7, 0, c10, 5);
CONTROL_REG_GEN_WRITE 433 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCCISW, c7, 0, c14, 2);
CONTROL_REG_GEN_WRITE 437 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ICIALLLUIS, c7, 0, c1, 0);
CONTROL_REG_GEN_WRITE 438 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(BPIALLIS, c7, 0, c1, 6);
CONTROL_REG_GEN_WRITE 440 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(PAR, c7, 0, c4, 0); /* Security Extensions */
CONTROL_REG_GEN_WRITE 441 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ICIALLU, c7, 0, c5, 0);
CONTROL_REG_GEN_WRITE 442 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ICIMVAU, c7, 0, c5, 1);
CONTROL_REG_GEN_WRITE 443 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCIMVAC, c7, 0, c6, 1);
CONTROL_REG_GEN_WRITE 445 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(PARH, c7, 0, c7, 0); /* PAE */
CONTROL_REG_GEN_WRITE 446 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0); /* Security Extensions */
CONTROL_REG_GEN_WRITE 447 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS1CPW, c7, 0, c8, 1); /* Security Extensions */
CONTROL_REG_GEN_WRITE 448 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2); /* Security Extensions */
CONTROL_REG_GEN_WRITE 449 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3); /* Security Extensions */
CONTROL_REG_GEN_WRITE 450 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS12NSOPR, c7, 0, c8, 4); /* Security Extensions */
CONTROL_REG_GEN_WRITE 451 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS12NSOPW, c7, 0, c8, 5); /* Security Extensions */
CONTROL_REG_GEN_WRITE 452 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS12NSOUR, c7, 0, c8, 6); /* Security Extensions */
CONTROL_REG_GEN_WRITE 453 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS12NSOUW, c7, 0, c8, 7); /* Security Extensions */
CONTROL_REG_GEN_WRITE 454 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS1HR, c7, 4, c8, 0); /* Virtualization Extensions */
CONTROL_REG_GEN_WRITE 455 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS1HW, c7, 4, c8, 1); /* Virtualization Extensions */
CONTROL_REG_GEN_WRITE 456 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCCMVAC, c7, 0, c10, 1);
CONTROL_REG_GEN_WRITE 457 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCCMVAU, c7, 0, c11, 1);
CONTROL_REG_GEN_WRITE 458 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCCIMVAC, c7, 0, c14, 1);
CONTROL_REG_GEN_WRITE 462 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(WFI, c7, 0, c0, 4);
CONTROL_REG_GEN_WRITE 465 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ICIALL, c7, 0, c5, 0);
CONTROL_REG_GEN_WRITE 466 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ICIMVA, c7, 0, c5, 1);
CONTROL_REG_GEN_WRITE 469 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ICISW, c7, 0, c5, 2);
CONTROL_REG_GEN_WRITE 472 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCIALL, c7, 0, c6, 0);
CONTROL_REG_GEN_WRITE 473 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCIMVA, c7, 0, c6, 1);
CONTROL_REG_GEN_WRITE 474 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CIALL, c7, 0, c7, 0);
CONTROL_REG_GEN_WRITE 475 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CIMVA, c7, 0, c7, 1);
CONTROL_REG_GEN_WRITE 478 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CISW, c7, 0, c7, 2);
CONTROL_REG_GEN_WRITE 482 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCCALL, c7, 0, c10, 0);
CONTROL_REG_GEN_WRITE 485 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCCMVA, c7, 0, c10, 1);
CONTROL_REG_GEN_WRITE 488 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CCALL, c7, 0, c11, 0);
CONTROL_REG_GEN_WRITE 491 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CCMVA, c7, 0, c11, 1);
CONTROL_REG_GEN_WRITE 494 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CCSW, c7, 0, c11, 2);
CONTROL_REG_GEN_WRITE 498 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(PFIMVA, c7, 0, c13, 1);
CONTROL_REG_GEN_WRITE 502 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCCIALL, c7, 0, c14, 0);
CONTROL_REG_GEN_WRITE 505 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCCIMVA, c7, 0, c14, 1);
CONTROL_REG_GEN_WRITE 508 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CCIALL, c7, 0, c15, 0);
CONTROL_REG_GEN_WRITE 511 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CCIMVA, c7, 0, c15, 1);
CONTROL_REG_GEN_WRITE 514 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CCISW, c7, 0, c15, 2);
CONTROL_REG_GEN_WRITE 521 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIALLIS, c8, 0, c3, 0); /* Inner shareable */
CONTROL_REG_GEN_WRITE 522 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIMVAIS, c8, 0, c3, 1); /* Inner shareable */
CONTROL_REG_GEN_WRITE 523 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIASIDIS, c8, 0, c3, 2); /* Inner shareable */
CONTROL_REG_GEN_WRITE 524 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIMVAAIS, c8, 0, c3, 3); /* Inner shareable */
CONTROL_REG_GEN_WRITE 527 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ITLBIALL, c8, 0, c5, 0);
CONTROL_REG_GEN_WRITE 528 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ITLBIMVA, c8, 0, c5, 1);
CONTROL_REG_GEN_WRITE 530 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ITLBIASID, c8, 0, c5, 2);
CONTROL_REG_GEN_WRITE 533 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DTLBIALL, c8, 0, c6, 0);
CONTROL_REG_GEN_WRITE 534 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DTLBIMVA, c8, 0, c6, 1);
CONTROL_REG_GEN_WRITE 536 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DTLBIASID, c8, 0, c6, 2);
CONTROL_REG_GEN_WRITE 539 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIALL, c8, 0, c7, 0);
CONTROL_REG_GEN_WRITE 540 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIMVA, c8, 0, c7, 1);
CONTROL_REG_GEN_WRITE 542 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIASID, c8, 0, c7, 2);
CONTROL_REG_GEN_WRITE 545 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIMVAA, c8, 0, c7, 3);
CONTROL_REG_GEN_WRITE 549 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIALLHIS, c8, 4, c3, 0); /* Inner shareable */
CONTROL_REG_GEN_WRITE 550 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIMVAHIS, c8, 4, c3, 1); /* Inner shareable */
CONTROL_REG_GEN_WRITE 551 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIALLNSNHIS, c8, 4, c3, 4); /* Inner shareable */
CONTROL_REG_GEN_WRITE 555 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIALLH, c8, 4, c7, 0);
CONTROL_REG_GEN_WRITE 556 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIMVAH, c8, 4, c7, 1);
CONTROL_REG_GEN_WRITE 557 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIALLNSNHS, c8, 4, c7, 4);
CONTROL_REG_GEN_WRITE 576 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(PMCR, c9, 0, c12, 0);
CONTROL_REG_GEN_WRITE 582 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(PMCNTENSET, c9, 0, c12, 1);
CONTROL_REG_GEN_WRITE 584 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(PMCCNTR, c9, 0, c13, 0);
CONTROL_REG_GEN_WRITE 588 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(PRRR, c10, 0, c2, 0); /* no PAE */
CONTROL_REG_GEN_WRITE 590 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(MAIR0, c10, 0, c2, 0); /* PAE */
CONTROL_REG_GEN_WRITE 592 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(NMRR, c10, 0, c2, 1); /* no PAE */
CONTROL_REG_GEN_WRITE 594 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(MAIR1, c10, 0, c2, 1); /* PAE */
CONTROL_REG_GEN_WRITE 597 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(AMAIR0, c10, 0, c3, 0); /* PAE */
CONTROL_REG_GEN_WRITE 599 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(AMAIR1, c10, 0, c3, 1); /* PAE */
CONTROL_REG_GEN_WRITE 602 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HMAIR0, c10, 4, c2, 0);
CONTROL_REG_GEN_WRITE 604 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HMAIR1, c10, 4, c2, 1);
CONTROL_REG_GEN_WRITE 607 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HAMAIR0, c10, 4, c3, 0);
CONTROL_REG_GEN_WRITE 609 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HAMAIR1, c10, 4, c3, 1);
CONTROL_REG_GEN_WRITE 615 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(VBAR, c12, 0, c0, 0);
CONTROL_REG_GEN_WRITE 617 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(MVBAR, c12, 0, c0, 1);
CONTROL_REG_GEN_WRITE 622 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HVBAR, c12, 4, c0, 0);
CONTROL_REG_GEN_WRITE 628 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CONTEXTIDR, c13, 0, c0, 1);
CONTROL_REG_GEN_WRITE 630 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TPIDRURW, c13, 0, c0, 2);
CONTROL_REG_GEN_WRITE 632 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TPIDRURO, c13, 0, c0, 3);
CONTROL_REG_GEN_WRITE 634 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TPIDRPRW, c13, 0, c0, 4);
CONTROL_REG_GEN_WRITE 637 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HTPIDR, c13, 4, c0, 2);
CONTROL_REG_GEN_WRITE 641 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CNTFRQ, c14, 0, c0, 0);
CONTROL_REG_GEN_WRITE 643 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CNTKCTL, c14, 0, c1, 0);
CONTROL_REG_GEN_WRITE 646 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CNTP_TVAL, c14, 0, c2, 0);
CONTROL_REG_GEN_WRITE 648 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CNTP_CTL, c14, 0, c2, 1);
CONTROL_REG_GEN_WRITE 651 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CNTV_TVAL, c14, 0, c3, 0);
CONTROL_REG_GEN_WRITE 653 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CNTV_CTL, c14, 0, c3, 1);
CONTROL_REG_GEN_WRITE 656 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CNTHCTL, c14, 4, c1, 0);
CONTROL_REG_GEN_WRITE 659 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CNTHP_TVAL, c14, 4, c2, 0);
CONTROL_REG_GEN_WRITE 661 boot/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CNTHP_CTL, c14, 4, c2, 1);
CONTROL_REG_GEN_WRITE 225 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CSSELR, c0, 2, c0, 0);
CONTROL_REG_GEN_WRITE 227 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(VPIDR, c0, 4, c0, 0);
CONTROL_REG_GEN_WRITE 229 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(VMPIDR, c0, 4, c0, 5);
CONTROL_REG_GEN_WRITE 261 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(SCTLR, c1, 0, c0, 0);
CONTROL_REG_GEN_WRITE 263 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ACTLR, c1, 0, c0, 1);
CONTROL_REG_GEN_WRITE 275 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CPACR, c1, 0, c0, 2);
CONTROL_REG_GEN_WRITE 291 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(SCR, c1, 0, c1, 0);
CONTROL_REG_GEN_WRITE 293 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(SDER, c1, 0, c1, 1);
CONTROL_REG_GEN_WRITE 303 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(NSACR, c1, 0, c1, 2);
CONTROL_REG_GEN_WRITE 307 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HSCTLR, c1, 4, c0, 0);
CONTROL_REG_GEN_WRITE 309 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HACTLR, c1, 4, c0, 1);
CONTROL_REG_GEN_WRITE 312 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HCR, c1, 4, c1, 0);
CONTROL_REG_GEN_WRITE 314 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HDCR, c1, 4, c1, 1);
CONTROL_REG_GEN_WRITE 316 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HCPTR, c1, 4, c1, 2);
CONTROL_REG_GEN_WRITE 318 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HSTR, c1, 4, c1, 3);
CONTROL_REG_GEN_WRITE 320 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HACR, c1, 4, c1, 7);
CONTROL_REG_GEN_WRITE 337 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0);
CONTROL_REG_GEN_WRITE 341 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TTBR1, c2, 0, c0, 1);
CONTROL_REG_GEN_WRITE 343 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TTBCR, c2, 0, c0, 2);
CONTROL_REG_GEN_WRITE 348 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HTCR, c2, 4, c0, 2);
CONTROL_REG_GEN_WRITE 350 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(VTCR, c2, 4, c1, 2);
CONTROL_REG_GEN_WRITE 354 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TTBR0H, c2, 0, c2, 0);
CONTROL_REG_GEN_WRITE 356 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TTBR1H, c2, 0, c2, 1);
CONTROL_REG_GEN_WRITE 358 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HTTBRH, c2, 0, c2, 4);
CONTROL_REG_GEN_WRITE 360 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(VTTBRH, c2, 0, c2, 6);
CONTROL_REG_GEN_WRITE 364 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DACR, c3, 0, c0, 0);
CONTROL_REG_GEN_WRITE 368 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DFSR, c5, 0, c0, 0);
CONTROL_REG_GEN_WRITE 370 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(IFSR, c5, 0, c0, 1);
CONTROL_REG_GEN_WRITE 373 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ADFSR, c5, 0, c1, 0);
CONTROL_REG_GEN_WRITE 375 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(AIFSR, c5, 0, c1, 1);
CONTROL_REG_GEN_WRITE 378 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HADFSR, c5, 4, c1, 0);
CONTROL_REG_GEN_WRITE 380 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HAIFSR, c5, 4, c1, 1);
CONTROL_REG_GEN_WRITE 382 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HSR, c5, 4, c2, 0);
CONTROL_REG_GEN_WRITE 385 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DFAR, c6, 0, c0, 0);
CONTROL_REG_GEN_WRITE 387 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(IFAR, c6, 0, c0, 2);
CONTROL_REG_GEN_WRITE 390 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HDFAR, c6, 4, c0, 0);
CONTROL_REG_GEN_WRITE 392 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HIFAR, c6, 4, c0, 2);
CONTROL_REG_GEN_WRITE 394 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HPFAR, c6, 4, c0, 4);
CONTROL_REG_GEN_WRITE 413 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CP15ISB, c7, 0, c5, 4);
CONTROL_REG_GEN_WRITE 414 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(BPIALL, c7, 0, c5, 6);
CONTROL_REG_GEN_WRITE 415 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(BPIMVA, c7, 0, c5, 7);
CONTROL_REG_GEN_WRITE 419 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCISW, c7, 0, c6, 2);
CONTROL_REG_GEN_WRITE 423 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCCSW, c7, 0, c10, 2);
CONTROL_REG_GEN_WRITE 426 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CP15DSB, c7, 0, c10, 4);
CONTROL_REG_GEN_WRITE 429 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CP15DMB, c7, 0, c10, 5);
CONTROL_REG_GEN_WRITE 433 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCCISW, c7, 0, c14, 2);
CONTROL_REG_GEN_WRITE 437 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ICIALLLUIS, c7, 0, c1, 0);
CONTROL_REG_GEN_WRITE 438 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(BPIALLIS, c7, 0, c1, 6);
CONTROL_REG_GEN_WRITE 440 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(PAR, c7, 0, c4, 0); /* Security Extensions */
CONTROL_REG_GEN_WRITE 441 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ICIALLU, c7, 0, c5, 0);
CONTROL_REG_GEN_WRITE 442 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ICIMVAU, c7, 0, c5, 1);
CONTROL_REG_GEN_WRITE 443 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCIMVAC, c7, 0, c6, 1);
CONTROL_REG_GEN_WRITE 445 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(PARH, c7, 0, c7, 0); /* PAE */
CONTROL_REG_GEN_WRITE 446 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0); /* Security Extensions */
CONTROL_REG_GEN_WRITE 447 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS1CPW, c7, 0, c8, 1); /* Security Extensions */
CONTROL_REG_GEN_WRITE 448 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2); /* Security Extensions */
CONTROL_REG_GEN_WRITE 449 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3); /* Security Extensions */
CONTROL_REG_GEN_WRITE 450 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS12NSOPR, c7, 0, c8, 4); /* Security Extensions */
CONTROL_REG_GEN_WRITE 451 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS12NSOPW, c7, 0, c8, 5); /* Security Extensions */
CONTROL_REG_GEN_WRITE 452 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS12NSOUR, c7, 0, c8, 6); /* Security Extensions */
CONTROL_REG_GEN_WRITE 453 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS12NSOUW, c7, 0, c8, 7); /* Security Extensions */
CONTROL_REG_GEN_WRITE 454 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS1HR, c7, 4, c8, 0); /* Virtualization Extensions */
CONTROL_REG_GEN_WRITE 455 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ATS1HW, c7, 4, c8, 1); /* Virtualization Extensions */
CONTROL_REG_GEN_WRITE 456 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCCMVAC, c7, 0, c10, 1);
CONTROL_REG_GEN_WRITE 457 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCCMVAU, c7, 0, c11, 1);
CONTROL_REG_GEN_WRITE 458 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCCIMVAC, c7, 0, c14, 1);
CONTROL_REG_GEN_WRITE 462 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(WFI, c7, 0, c0, 4);
CONTROL_REG_GEN_WRITE 465 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ICIALL, c7, 0, c5, 0);
CONTROL_REG_GEN_WRITE 466 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ICIMVA, c7, 0, c5, 1);
CONTROL_REG_GEN_WRITE 469 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ICISW, c7, 0, c5, 2);
CONTROL_REG_GEN_WRITE 472 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCIALL, c7, 0, c6, 0);
CONTROL_REG_GEN_WRITE 473 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCIMVA, c7, 0, c6, 1);
CONTROL_REG_GEN_WRITE 474 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CIALL, c7, 0, c7, 0);
CONTROL_REG_GEN_WRITE 475 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CIMVA, c7, 0, c7, 1);
CONTROL_REG_GEN_WRITE 478 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CISW, c7, 0, c7, 2);
CONTROL_REG_GEN_WRITE 482 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCCALL, c7, 0, c10, 0);
CONTROL_REG_GEN_WRITE 485 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCCMVA, c7, 0, c10, 1);
CONTROL_REG_GEN_WRITE 488 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CCALL, c7, 0, c11, 0);
CONTROL_REG_GEN_WRITE 491 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CCMVA, c7, 0, c11, 1);
CONTROL_REG_GEN_WRITE 494 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CCSW, c7, 0, c11, 2);
CONTROL_REG_GEN_WRITE 498 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(PFIMVA, c7, 0, c13, 1);
CONTROL_REG_GEN_WRITE 502 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCCIALL, c7, 0, c14, 0);
CONTROL_REG_GEN_WRITE 505 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DCCIMVA, c7, 0, c14, 1);
CONTROL_REG_GEN_WRITE 508 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CCIALL, c7, 0, c15, 0);
CONTROL_REG_GEN_WRITE 511 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CCIMVA, c7, 0, c15, 1);
CONTROL_REG_GEN_WRITE 514 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CCISW, c7, 0, c15, 2);
CONTROL_REG_GEN_WRITE 521 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIALLIS, c8, 0, c3, 0); /* Inner shareable */
CONTROL_REG_GEN_WRITE 522 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIMVAIS, c8, 0, c3, 1); /* Inner shareable */
CONTROL_REG_GEN_WRITE 523 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIASIDIS, c8, 0, c3, 2); /* Inner shareable */
CONTROL_REG_GEN_WRITE 524 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIMVAAIS, c8, 0, c3, 3); /* Inner shareable */
CONTROL_REG_GEN_WRITE 527 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ITLBIALL, c8, 0, c5, 0);
CONTROL_REG_GEN_WRITE 528 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ITLBIMVA, c8, 0, c5, 1);
CONTROL_REG_GEN_WRITE 530 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(ITLBIASID, c8, 0, c5, 2);
CONTROL_REG_GEN_WRITE 533 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DTLBIALL, c8, 0, c6, 0);
CONTROL_REG_GEN_WRITE 534 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DTLBIMVA, c8, 0, c6, 1);
CONTROL_REG_GEN_WRITE 536 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(DTLBIASID, c8, 0, c6, 2);
CONTROL_REG_GEN_WRITE 539 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIALL, c8, 0, c7, 0);
CONTROL_REG_GEN_WRITE 540 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIMVA, c8, 0, c7, 1);
CONTROL_REG_GEN_WRITE 542 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIASID, c8, 0, c7, 2);
CONTROL_REG_GEN_WRITE 545 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIMVAA, c8, 0, c7, 3);
CONTROL_REG_GEN_WRITE 549 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIALLHIS, c8, 4, c3, 0); /* Inner shareable */
CONTROL_REG_GEN_WRITE 550 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIMVAHIS, c8, 4, c3, 1); /* Inner shareable */
CONTROL_REG_GEN_WRITE 551 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIALLNSNHIS, c8, 4, c3, 4); /* Inner shareable */
CONTROL_REG_GEN_WRITE 555 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIALLH, c8, 4, c7, 0);
CONTROL_REG_GEN_WRITE 556 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIMVAH, c8, 4, c7, 1);
CONTROL_REG_GEN_WRITE 557 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TLBIALLNSNHS, c8, 4, c7, 4);
CONTROL_REG_GEN_WRITE 576 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(PMCR, c9, 0, c12, 0);
CONTROL_REG_GEN_WRITE 582 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(PMCNTENSET, c9, 0, c12, 1);
CONTROL_REG_GEN_WRITE 584 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(PMCCNTR, c9, 0, c13, 0);
CONTROL_REG_GEN_WRITE 588 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(PRRR, c10, 0, c2, 0); /* no PAE */
CONTROL_REG_GEN_WRITE 590 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(MAIR0, c10, 0, c2, 0); /* PAE */
CONTROL_REG_GEN_WRITE 592 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(NMRR, c10, 0, c2, 1); /* no PAE */
CONTROL_REG_GEN_WRITE 594 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(MAIR1, c10, 0, c2, 1); /* PAE */
CONTROL_REG_GEN_WRITE 597 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(AMAIR0, c10, 0, c3, 0); /* PAE */
CONTROL_REG_GEN_WRITE 599 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(AMAIR1, c10, 0, c3, 1); /* PAE */
CONTROL_REG_GEN_WRITE 602 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HMAIR0, c10, 4, c2, 0);
CONTROL_REG_GEN_WRITE 604 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HMAIR1, c10, 4, c2, 1);
CONTROL_REG_GEN_WRITE 607 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HAMAIR0, c10, 4, c3, 0);
CONTROL_REG_GEN_WRITE 609 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HAMAIR1, c10, 4, c3, 1);
CONTROL_REG_GEN_WRITE 615 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(VBAR, c12, 0, c0, 0);
CONTROL_REG_GEN_WRITE 617 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(MVBAR, c12, 0, c0, 1);
CONTROL_REG_GEN_WRITE 622 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HVBAR, c12, 4, c0, 0);
CONTROL_REG_GEN_WRITE 628 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CONTEXTIDR, c13, 0, c0, 1);
CONTROL_REG_GEN_WRITE 630 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TPIDRURW, c13, 0, c0, 2);
CONTROL_REG_GEN_WRITE 632 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TPIDRURO, c13, 0, c0, 3);
CONTROL_REG_GEN_WRITE 634 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(TPIDRPRW, c13, 0, c0, 4);
CONTROL_REG_GEN_WRITE 637 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(HTPIDR, c13, 4, c0, 2);
CONTROL_REG_GEN_WRITE 641 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CNTFRQ, c14, 0, c0, 0);
CONTROL_REG_GEN_WRITE 643 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CNTKCTL, c14, 0, c1, 0);
CONTROL_REG_GEN_WRITE 646 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CNTP_TVAL, c14, 0, c2, 0);
CONTROL_REG_GEN_WRITE 648 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CNTP_CTL, c14, 0, c2, 1);
CONTROL_REG_GEN_WRITE 651 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CNTV_TVAL, c14, 0, c3, 0);
CONTROL_REG_GEN_WRITE 653 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CNTV_CTL, c14, 0, c3, 1);
CONTROL_REG_GEN_WRITE 656 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CNTHCTL, c14, 4, c1, 0);
CONTROL_REG_GEN_WRITE 659 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CNTHP_TVAL, c14, 4, c2, 0);
CONTROL_REG_GEN_WRITE 661 kernel/arch/arm32/include/arch/cp15.h CONTROL_REG_GEN_WRITE(CNTHP_CTL, c14, 4, c2, 1);
CONTROL_REG_GEN_WRITE 225 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CSSELR, c0, 2, c0, 0);
CONTROL_REG_GEN_WRITE 227 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(VPIDR, c0, 4, c0, 0);
CONTROL_REG_GEN_WRITE 229 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(VMPIDR, c0, 4, c0, 5);
CONTROL_REG_GEN_WRITE 261 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(SCTLR, c1, 0, c0, 0);
CONTROL_REG_GEN_WRITE 263 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ACTLR, c1, 0, c0, 1);
CONTROL_REG_GEN_WRITE 275 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CPACR, c1, 0, c0, 2);
CONTROL_REG_GEN_WRITE 291 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(SCR, c1, 0, c1, 0);
CONTROL_REG_GEN_WRITE 293 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(SDER, c1, 0, c1, 1);
CONTROL_REG_GEN_WRITE 303 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(NSACR, c1, 0, c1, 2);
CONTROL_REG_GEN_WRITE 307 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HSCTLR, c1, 4, c0, 0);
CONTROL_REG_GEN_WRITE 309 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HACTLR, c1, 4, c0, 1);
CONTROL_REG_GEN_WRITE 312 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HCR, c1, 4, c1, 0);
CONTROL_REG_GEN_WRITE 314 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HDCR, c1, 4, c1, 1);
CONTROL_REG_GEN_WRITE 316 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HCPTR, c1, 4, c1, 2);
CONTROL_REG_GEN_WRITE 318 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HSTR, c1, 4, c1, 3);
CONTROL_REG_GEN_WRITE 320 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HACR, c1, 4, c1, 7);
CONTROL_REG_GEN_WRITE 337 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0);
CONTROL_REG_GEN_WRITE 341 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TTBR1, c2, 0, c0, 1);
CONTROL_REG_GEN_WRITE 343 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TTBCR, c2, 0, c0, 2);
CONTROL_REG_GEN_WRITE 348 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HTCR, c2, 4, c0, 2);
CONTROL_REG_GEN_WRITE 350 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(VTCR, c2, 4, c1, 2);
CONTROL_REG_GEN_WRITE 354 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TTBR0H, c2, 0, c2, 0);
CONTROL_REG_GEN_WRITE 356 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TTBR1H, c2, 0, c2, 1);
CONTROL_REG_GEN_WRITE 358 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HTTBRH, c2, 0, c2, 4);
CONTROL_REG_GEN_WRITE 360 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(VTTBRH, c2, 0, c2, 6);
CONTROL_REG_GEN_WRITE 364 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DACR, c3, 0, c0, 0);
CONTROL_REG_GEN_WRITE 368 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DFSR, c5, 0, c0, 0);
CONTROL_REG_GEN_WRITE 370 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(IFSR, c5, 0, c0, 1);
CONTROL_REG_GEN_WRITE 373 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ADFSR, c5, 0, c1, 0);
CONTROL_REG_GEN_WRITE 375 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(AIFSR, c5, 0, c1, 1);
CONTROL_REG_GEN_WRITE 378 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HADFSR, c5, 4, c1, 0);
CONTROL_REG_GEN_WRITE 380 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HAIFSR, c5, 4, c1, 1);
CONTROL_REG_GEN_WRITE 382 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HSR, c5, 4, c2, 0);
CONTROL_REG_GEN_WRITE 385 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DFAR, c6, 0, c0, 0);
CONTROL_REG_GEN_WRITE 387 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(IFAR, c6, 0, c0, 2);
CONTROL_REG_GEN_WRITE 390 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HDFAR, c6, 4, c0, 0);
CONTROL_REG_GEN_WRITE 392 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HIFAR, c6, 4, c0, 2);
CONTROL_REG_GEN_WRITE 394 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HPFAR, c6, 4, c0, 4);
CONTROL_REG_GEN_WRITE 413 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CP15ISB, c7, 0, c5, 4);
CONTROL_REG_GEN_WRITE 414 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(BPIALL, c7, 0, c5, 6);
CONTROL_REG_GEN_WRITE 415 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(BPIMVA, c7, 0, c5, 7);
CONTROL_REG_GEN_WRITE 419 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DCISW, c7, 0, c6, 2);
CONTROL_REG_GEN_WRITE 423 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DCCSW, c7, 0, c10, 2);
CONTROL_REG_GEN_WRITE 426 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CP15DSB, c7, 0, c10, 4);
CONTROL_REG_GEN_WRITE 429 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CP15DMB, c7, 0, c10, 5);
CONTROL_REG_GEN_WRITE 433 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DCCISW, c7, 0, c14, 2);
CONTROL_REG_GEN_WRITE 437 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ICIALLLUIS, c7, 0, c1, 0);
CONTROL_REG_GEN_WRITE 438 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(BPIALLIS, c7, 0, c1, 6);
CONTROL_REG_GEN_WRITE 440 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(PAR, c7, 0, c4, 0); /* Security Extensions */
CONTROL_REG_GEN_WRITE 441 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ICIALLU, c7, 0, c5, 0);
CONTROL_REG_GEN_WRITE 442 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ICIMVAU, c7, 0, c5, 1);
CONTROL_REG_GEN_WRITE 443 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DCIMVAC, c7, 0, c6, 1);
CONTROL_REG_GEN_WRITE 445 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(PARH, c7, 0, c7, 0); /* PAE */
CONTROL_REG_GEN_WRITE 446 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0); /* Security Extensions */
CONTROL_REG_GEN_WRITE 447 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ATS1CPW, c7, 0, c8, 1); /* Security Extensions */
CONTROL_REG_GEN_WRITE 448 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2); /* Security Extensions */
CONTROL_REG_GEN_WRITE 449 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3); /* Security Extensions */
CONTROL_REG_GEN_WRITE 450 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ATS12NSOPR, c7, 0, c8, 4); /* Security Extensions */
CONTROL_REG_GEN_WRITE 451 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ATS12NSOPW, c7, 0, c8, 5); /* Security Extensions */
CONTROL_REG_GEN_WRITE 452 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ATS12NSOUR, c7, 0, c8, 6); /* Security Extensions */
CONTROL_REG_GEN_WRITE 453 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ATS12NSOUW, c7, 0, c8, 7); /* Security Extensions */
CONTROL_REG_GEN_WRITE 454 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ATS1HR, c7, 4, c8, 0); /* Virtualization Extensions */
CONTROL_REG_GEN_WRITE 455 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ATS1HW, c7, 4, c8, 1); /* Virtualization Extensions */
CONTROL_REG_GEN_WRITE 456 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DCCMVAC, c7, 0, c10, 1);
CONTROL_REG_GEN_WRITE 457 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DCCMVAU, c7, 0, c11, 1);
CONTROL_REG_GEN_WRITE 458 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DCCIMVAC, c7, 0, c14, 1);
CONTROL_REG_GEN_WRITE 462 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(WFI, c7, 0, c0, 4);
CONTROL_REG_GEN_WRITE 465 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ICIALL, c7, 0, c5, 0);
CONTROL_REG_GEN_WRITE 466 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ICIMVA, c7, 0, c5, 1);
CONTROL_REG_GEN_WRITE 469 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ICISW, c7, 0, c5, 2);
CONTROL_REG_GEN_WRITE 472 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DCIALL, c7, 0, c6, 0);
CONTROL_REG_GEN_WRITE 473 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DCIMVA, c7, 0, c6, 1);
CONTROL_REG_GEN_WRITE 474 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CIALL, c7, 0, c7, 0);
CONTROL_REG_GEN_WRITE 475 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CIMVA, c7, 0, c7, 1);
CONTROL_REG_GEN_WRITE 478 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CISW, c7, 0, c7, 2);
CONTROL_REG_GEN_WRITE 482 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DCCALL, c7, 0, c10, 0);
CONTROL_REG_GEN_WRITE 485 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DCCMVA, c7, 0, c10, 1);
CONTROL_REG_GEN_WRITE 488 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CCALL, c7, 0, c11, 0);
CONTROL_REG_GEN_WRITE 491 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CCMVA, c7, 0, c11, 1);
CONTROL_REG_GEN_WRITE 494 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CCSW, c7, 0, c11, 2);
CONTROL_REG_GEN_WRITE 498 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(PFIMVA, c7, 0, c13, 1);
CONTROL_REG_GEN_WRITE 502 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DCCIALL, c7, 0, c14, 0);
CONTROL_REG_GEN_WRITE 505 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DCCIMVA, c7, 0, c14, 1);
CONTROL_REG_GEN_WRITE 508 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CCIALL, c7, 0, c15, 0);
CONTROL_REG_GEN_WRITE 511 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CCIMVA, c7, 0, c15, 1);
CONTROL_REG_GEN_WRITE 514 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CCISW, c7, 0, c15, 2);
CONTROL_REG_GEN_WRITE 521 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TLBIALLIS, c8, 0, c3, 0); /* Inner shareable */
CONTROL_REG_GEN_WRITE 522 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TLBIMVAIS, c8, 0, c3, 1); /* Inner shareable */
CONTROL_REG_GEN_WRITE 523 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TLBIASIDIS, c8, 0, c3, 2); /* Inner shareable */
CONTROL_REG_GEN_WRITE 524 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TLBIMVAAIS, c8, 0, c3, 3); /* Inner shareable */
CONTROL_REG_GEN_WRITE 527 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ITLBIALL, c8, 0, c5, 0);
CONTROL_REG_GEN_WRITE 528 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ITLBIMVA, c8, 0, c5, 1);
CONTROL_REG_GEN_WRITE 530 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(ITLBIASID, c8, 0, c5, 2);
CONTROL_REG_GEN_WRITE 533 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DTLBIALL, c8, 0, c6, 0);
CONTROL_REG_GEN_WRITE 534 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DTLBIMVA, c8, 0, c6, 1);
CONTROL_REG_GEN_WRITE 536 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(DTLBIASID, c8, 0, c6, 2);
CONTROL_REG_GEN_WRITE 539 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TLBIALL, c8, 0, c7, 0);
CONTROL_REG_GEN_WRITE 540 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TLBIMVA, c8, 0, c7, 1);
CONTROL_REG_GEN_WRITE 542 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TLBIASID, c8, 0, c7, 2);
CONTROL_REG_GEN_WRITE 545 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TLBIMVAA, c8, 0, c7, 3);
CONTROL_REG_GEN_WRITE 549 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TLBIALLHIS, c8, 4, c3, 0); /* Inner shareable */
CONTROL_REG_GEN_WRITE 550 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TLBIMVAHIS, c8, 4, c3, 1); /* Inner shareable */
CONTROL_REG_GEN_WRITE 551 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TLBIALLNSNHIS, c8, 4, c3, 4); /* Inner shareable */
CONTROL_REG_GEN_WRITE 555 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TLBIALLH, c8, 4, c7, 0);
CONTROL_REG_GEN_WRITE 556 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TLBIMVAH, c8, 4, c7, 1);
CONTROL_REG_GEN_WRITE 557 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TLBIALLNSNHS, c8, 4, c7, 4);
CONTROL_REG_GEN_WRITE 576 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(PMCR, c9, 0, c12, 0);
CONTROL_REG_GEN_WRITE 582 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(PMCNTENSET, c9, 0, c12, 1);
CONTROL_REG_GEN_WRITE 584 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(PMCCNTR, c9, 0, c13, 0);
CONTROL_REG_GEN_WRITE 588 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(PRRR, c10, 0, c2, 0); /* no PAE */
CONTROL_REG_GEN_WRITE 590 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(MAIR0, c10, 0, c2, 0); /* PAE */
CONTROL_REG_GEN_WRITE 592 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(NMRR, c10, 0, c2, 1); /* no PAE */
CONTROL_REG_GEN_WRITE 594 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(MAIR1, c10, 0, c2, 1); /* PAE */
CONTROL_REG_GEN_WRITE 597 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(AMAIR0, c10, 0, c3, 0); /* PAE */
CONTROL_REG_GEN_WRITE 599 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(AMAIR1, c10, 0, c3, 1); /* PAE */
CONTROL_REG_GEN_WRITE 602 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HMAIR0, c10, 4, c2, 0);
CONTROL_REG_GEN_WRITE 604 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HMAIR1, c10, 4, c2, 1);
CONTROL_REG_GEN_WRITE 607 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HAMAIR0, c10, 4, c3, 0);
CONTROL_REG_GEN_WRITE 609 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HAMAIR1, c10, 4, c3, 1);
CONTROL_REG_GEN_WRITE 615 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(VBAR, c12, 0, c0, 0);
CONTROL_REG_GEN_WRITE 617 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(MVBAR, c12, 0, c0, 1);
CONTROL_REG_GEN_WRITE 622 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HVBAR, c12, 4, c0, 0);
CONTROL_REG_GEN_WRITE 628 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CONTEXTIDR, c13, 0, c0, 1);
CONTROL_REG_GEN_WRITE 630 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TPIDRURW, c13, 0, c0, 2);
CONTROL_REG_GEN_WRITE 632 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TPIDRURO, c13, 0, c0, 3);
CONTROL_REG_GEN_WRITE 634 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(TPIDRPRW, c13, 0, c0, 4);
CONTROL_REG_GEN_WRITE 637 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(HTPIDR, c13, 4, c0, 2);
CONTROL_REG_GEN_WRITE 641 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CNTFRQ, c14, 0, c0, 0);
CONTROL_REG_GEN_WRITE 643 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CNTKCTL, c14, 0, c1, 0);
CONTROL_REG_GEN_WRITE 646 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CNTP_TVAL, c14, 0, c2, 0);
CONTROL_REG_GEN_WRITE 648 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CNTP_CTL, c14, 0, c2, 1);
CONTROL_REG_GEN_WRITE 651 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CNTV_TVAL, c14, 0, c3, 0);
CONTROL_REG_GEN_WRITE 653 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CNTV_CTL, c14, 0, c3, 1);
CONTROL_REG_GEN_WRITE 656 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CNTHCTL, c14, 4, c1, 0);
CONTROL_REG_GEN_WRITE 659 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CNTHP_TVAL, c14, 4, c2, 0);
CONTROL_REG_GEN_WRITE 661 uspace/lib/c/arch/arm32/include/libarch/cp15.h CONTROL_REG_GEN_WRITE(CNTHP_CTL, c14, 4, c2, 1);
HelenOS homepage, sources at GitHub