HelenOS sources

root/kernel/arch/ia64/include/arch/asm.h

INCLUDED FROM

DEFINITIONS

1. cpu_spin_hint
2. p2a
3. pio_write_8
4. pio_write_16
5. pio_write_32
6. pio_read_8
7. pio_read_16
8. pio_read_32
9. psr_read
10. iva_read
11. iva_write
12. ivr_read
13. cr64_read
14. itc_write
15. itc_read
16. itm_write
17. itm_read
18. itv_read
19. itv_write
20. eoi_write
21. tpr_read
22. tpr_write
23. interrupts_disable
24. interrupts_enable
25. interrupts_restore
26. interrupts_read
27. interrupts_disabled
28. pk_disable
29. cpu_interruptible_sleep

/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/** @addtogroup kernel_ia64
 * @{
 */
/** @file
 */

#ifndef KERN_ia64_ASM_H_
#define KERN_ia64_ASM_H_

#include <config.h>
#include <typedefs.h>
#include <arch/register.h>
#include <arch/legacyio.h>
#include <trace.h>

#define IO_SPACE_BOUNDARY       ((void *) (64 * 1024))

_NO_TRACE static inline void cpu_spin_hint(void)
{
}

/** Map the I/O port address to a legacy I/O address. */
_NO_TRACE static inline uintptr_t p2a(volatile void *p)
{
        uintptr_t prt = (uintptr_t) p;

        return legacyio_virt_base + (((prt >> 2) << 12) | (prt & 0xfff));
}

_NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
{
        if (port < (ioport8_t *) IO_SPACE_BOUNDARY)
                *((ioport8_t *) p2a(port)) = v;
        else
                *port = v;

        asm volatile (
            "mf\n"
            "mf.a\n"
            ::: "memory"
        );
}

_NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
{
        if (port < (ioport16_t *) IO_SPACE_BOUNDARY)
                *((ioport16_t *) p2a(port)) = v;
        else
                *port = v;

        asm volatile (
            "mf\n"
            "mf.a\n"
            ::: "memory"
        );
}

_NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
{
        if (port < (ioport32_t *) IO_SPACE_BOUNDARY)
                *((ioport32_t *) p2a(port)) = v;
        else
                *port = v;

        asm volatile (
            "mf\n"
            "mf.a\n"
            ::: "memory"
        );
}

_NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
{
        uint8_t v;

        asm volatile (
            "mf\n"
            ::: "memory"
        );

        if (port < (ioport8_t *) IO_SPACE_BOUNDARY)
                v = *((ioport8_t *) p2a(port));
        else
                v = *port;

        asm volatile (
            "mf.a\n"
            ::: "memory"
        );

        return v;
}

_NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
{
        uint16_t v;

        asm volatile (
            "mf\n"
            ::: "memory"
        );

        if (port < (ioport16_t *) IO_SPACE_BOUNDARY)
                v = *((ioport16_t *) p2a(port));
        else
                v = *port;

        asm volatile (
            "mf.a\n"
            ::: "memory"
        );

        return v;
}

_NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
{
        uint32_t v;

        asm volatile (
            "mf\n"
            ::: "memory"
        );

        if (port < (ioport32_t *) IO_SPACE_BOUNDARY)
                v = *((ioport32_t *) p2a(port));
        else
                v = *port;

        asm volatile (
            "mf.a\n"
            ::: "memory"
        );

        return v;
}

/** Return Processor State Register.
 *
 * @return PSR.
 *
 */
_NO_TRACE static inline uint64_t psr_read(void)
{
        uint64_t v;

        asm volatile (
            "mov %[value] = psr\n"
            : [value] "=r" (v)
        );

        return v;
}

/** Read IVA (Interruption Vector Address).
 *
 * @return Return location of interruption vector table.
 *
 */
_NO_TRACE static inline uint64_t iva_read(void)
{
        uint64_t v;

        asm volatile (
            "mov %[value] = cr.iva\n"
            : [value] "=r" (v)
        );

        return v;
}

/** Write IVA (Interruption Vector Address) register.
 *
 * @param v New location of interruption vector table.
 *
 */
_NO_TRACE static inline void iva_write(uint64_t v)
{
        asm volatile (
            "mov cr.iva = %[value]\n"
            :: [value] "r" (v)
        );
}

/** Read IVR (External Interrupt Vector Register).
 *
 * @return Highest priority, pending, unmasked external
 *         interrupt vector.
 *
 */
_NO_TRACE static inline uint64_t ivr_read(void)
{
        uint64_t v;

        asm volatile (
            "mov %[value] = cr.ivr\n"
            : [value] "=r" (v)
        );

        return v;
}

_NO_TRACE static inline uint64_t cr64_read(void)
{
        uint64_t v;

        asm volatile (
            "mov %[value] = cr64\n"
            : [value] "=r" (v)
        );

        return v;
}

/** Write ITC (Interval Timer Counter) register.
 *
 * @param v New counter value.
 *
 */
_NO_TRACE static inline void itc_write(uint64_t v)
{
        asm volatile (
            "mov ar.itc = %[value]\n"
            :: [value] "r" (v)
        );
}

/** Read ITC (Interval Timer Counter) register.
 *
 * @return Current counter value.
 *
 */
_NO_TRACE static inline uint64_t itc_read(void)
{
        uint64_t v;

        asm volatile (
            "mov %[value] = ar.itc\n"
            : [value] "=r" (v)
        );

        return v;
}

/** Write ITM (Interval Timer Match) register.
 *
 * @param v New match value.
 *
 */
_NO_TRACE static inline void itm_write(uint64_t v)
{
        asm volatile (
            "mov cr.itm = %[value]\n"
            :: [value] "r" (v)
        );
}

/** Read ITM (Interval Timer Match) register.
 *
 * @return Match value.
 *
 */
_NO_TRACE static inline uint64_t itm_read(void)
{
        uint64_t v;

        asm volatile (
            "mov %[value] = cr.itm\n"
            : [value] "=r" (v)
        );

        return v;
}

/** Read ITV (Interval Timer Vector) register.
 *
 * @return Current vector and mask bit.
 *
 */
_NO_TRACE static inline uint64_t itv_read(void)
{
        uint64_t v;

        asm volatile (
            "mov %[value] = cr.itv\n"
            : [value] "=r" (v)
        );

        return v;
}

/** Write ITV (Interval Timer Vector) register.
 *
 * @param v New vector and mask bit.
 *
 */
_NO_TRACE static inline void itv_write(uint64_t v)
{
        asm volatile (
            "mov cr.itv = %[value]\n"
            :: [value] "r" (v)
        );
}

/** Write EOI (End Of Interrupt) register.
 *
 * @param v This value is ignored.
 *
 */
_NO_TRACE static inline void eoi_write(uint64_t v)
{
        asm volatile (
            "mov cr.eoi = %[value]\n"
            :: [value] "r" (v)
        );
}

/** Read TPR (Task Priority Register).
 *
 * @return Current value of TPR.
 *
 */
_NO_TRACE static inline uint64_t tpr_read(void)
{
        uint64_t v;

        asm volatile (
            "mov %[value] = cr.tpr\n"
            : [value] "=r" (v)
        );

        return v;
}

/** Write TPR (Task Priority Register).
 *
 * @param v New value of TPR.
 *
 */
_NO_TRACE static inline void tpr_write(uint64_t v)
{
        asm volatile (
            "mov cr.tpr = %[value]\n"
            :: [value] "r" (v)
        );
}

/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of PSR.
 *
 * @return Old interrupt priority level.
 *
 */
_NO_TRACE static ipl_t interrupts_disable(void)
{
        uint64_t v;

        asm volatile (
            "mov %[value] = psr\n"
            "rsm %[mask]\n"
            : [value] "=r" (v)
            : [mask] "i" (PSR_I_MASK)
        );

        return (ipl_t) v;
}

/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of PSR.
 *
 * @return Old interrupt priority level.
 *
 */
_NO_TRACE static ipl_t interrupts_enable(void)
{
        uint64_t v;

        asm volatile (
            "mov %[value] = psr\n"
            "ssm %[mask]\n"
            ";;\n"
            "srlz.d\n"
            : [value] "=r" (v)
            : [mask] "i" (PSR_I_MASK)
        );

        return (ipl_t) v;
}

/** Restore interrupt priority level.
 *
 * Restore PSR.
 *
 * @param ipl Saved interrupt priority level.
 *
 */
_NO_TRACE static inline void interrupts_restore(ipl_t ipl)
{
        if (ipl & PSR_I_MASK)
                (void) interrupts_enable();
        else
                (void) interrupts_disable();
}

/** Return interrupt priority level.
 *
 * @return PSR.
 *
 */
_NO_TRACE static inline ipl_t interrupts_read(void)
{
        return (ipl_t) psr_read();
}

/** Check interrupts state.
 *
 * @return True if interrupts are disabled.
 *
 */
_NO_TRACE static inline bool interrupts_disabled(void)
{
        return !(psr_read() & PSR_I_MASK);
}

/** Disable protection key checking. */
_NO_TRACE static inline void pk_disable(void)
{
        asm volatile (
            "rsm %[mask]\n"
            ";;\n"
            "srlz.d\n"
            :: [mask] "i" (PSR_PK_MASK)
        );
}

extern void cpu_halt(void) __attribute__((noreturn));
extern void cpu_sleep(void);
extern void asm_delay_loop(uint32_t t);

extern void switch_to_userspace(uintptr_t, uintptr_t, uintptr_t, uintptr_t,
    uint64_t, uint64_t);

/** Enables interrupts and blocks until an interrupt arrives,
 * atomically if possible on target architecture.
 * Disables interrupts again before returning to caller.
 */
_NO_TRACE static inline void cpu_interruptible_sleep(void)
{
        // FIXME: do this properly
        interrupts_enable();
        cpu_sleep();
        interrupts_disable();
}

#endif

/** @}
 */