HelenOS sources

MMU_PAGE_WIDTH     54 kernel/arch/sparc64/include/arch/mm/page.h #define MMU_PAGES_PER_PAGE	(1 << (PAGE_WIDTH - MMU_PAGE_WIDTH))
MMU_PAGE_WIDTH     46 kernel/arch/sparc64/include/arch/mm/sun4v/page.h #define MMU_PAGES_PER_PAGE	(1 << (PAGE_WIDTH - MMU_PAGE_WIDTH))
MMU_PAGE_WIDTH    159 kernel/arch/sparc64/src/mm/sun4u/as.c 	tsb_base_reg.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH;
MMU_PAGE_WIDTH    161 kernel/arch/sparc64/src/mm/sun4u/as.c 	tsb_base_reg.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH;
MMU_PAGE_WIDTH    137 kernel/arch/sparc64/src/mm/sun4u/tlb.c 	pg.address = t->page + (index << MMU_PAGE_WIDTH);
MMU_PAGE_WIDTH    138 kernel/arch/sparc64/src/mm/sun4u/tlb.c 	fr.address = t->frame + (index << MMU_PAGE_WIDTH);
MMU_PAGE_WIDTH    174 kernel/arch/sparc64/src/mm/sun4u/tlb.c 	pg.address = t->page + (index << MMU_PAGE_WIDTH);
MMU_PAGE_WIDTH    175 kernel/arch/sparc64/src/mm/sun4u/tlb.c 	fr.address = t->frame + (index << MMU_PAGE_WIDTH);
MMU_PAGE_WIDTH    199 kernel/arch/sparc64/src/mm/sun4u/tlb.c 	size_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;
MMU_PAGE_WIDTH    243 kernel/arch/sparc64/src/mm/sun4u/tlb.c 	page_8k = (uint64_t) tag.vpn << MMU_PAGE_WIDTH;
MMU_PAGE_WIDTH    296 kernel/arch/sparc64/src/mm/sun4u/tlb.c 	page_16k = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
MMU_PAGE_WIDTH     63 kernel/arch/sparc64/src/mm/sun4u/tsb.c 	i0 = (page >> MMU_PAGE_WIDTH) & ITSB_ENTRY_MASK;
MMU_PAGE_WIDTH     90 kernel/arch/sparc64/src/mm/sun4u/tsb.c 	entry = ((t->page >> MMU_PAGE_WIDTH) + index) & ITSB_ENTRY_MASK;
MMU_PAGE_WIDTH    134 kernel/arch/sparc64/src/mm/sun4u/tsb.c 	entry = ((t->page >> MMU_PAGE_WIDTH) + index) & DTSB_ENTRY_MASK;
MMU_PAGE_WIDTH     64 kernel/arch/sparc64/src/mm/sun4v/tsb.c 	i0 = (page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK;
MMU_PAGE_WIDTH     88 kernel/arch/sparc64/src/mm/sun4v/tsb.c 	index = (t->page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK;
MMU_PAGE_WIDTH    135 kernel/arch/sparc64/src/mm/sun4v/tsb.c 	index = (t->page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK;