HelenOS sources
#ifndef KERN_arm64_REGUTILS_H_
#define KERN_arm64_REGUTILS_H_
#ifndef __ASSEMBLER__
#include <stdint.h>
#define SPECIAL_REG_GEN_READ(name) \
static inline uint64_t name##_read(void) \
{ \
uint64_t res; \
asm volatile ( \
"mrs %[res], " #name \
: [res] "=r" (res) \
); \
return res; \
}
#define SPECIAL_REG_GEN_WRITE(name) \
static inline void name##_write(uint64_t regn) \
{ \
asm volatile ( \
"msr " #name ", %[regn]\n" \
"isb\n" \
:: [regn] "r" (regn) \
); \
}
#define UWORD64(c) UINT64_C(c)
#else
#define SPECIAL_REG_GEN_READ(name)
#define SPECIAL_REG_GEN_WRITE(name)
#define UWORD64(c) c
#endif
SPECIAL_REG_GEN_READ(CNTFRQ_EL0);
SPECIAL_REG_GEN_READ(CNTVCT_EL0);
SPECIAL_REG_GEN_READ(CNTV_CTL_EL0);
SPECIAL_REG_GEN_WRITE(CNTV_CTL_EL0);
#define CNTV_CTL_ENABLE_SHIFT 0
#define CNTV_CTL_ENABLE_FLAG (UWORD64(1) << CNTV_CTL_ENABLE_SHIFT)
#define CNTV_CTL_IMASK_SHIFT 1
#define CNTV_CTL_IMASK_FLAG (UWORD64(1) << CNTV_CTL_IMASK_SHIFT)
SPECIAL_REG_GEN_READ(CNTV_CVAL_EL0);
SPECIAL_REG_GEN_WRITE(CNTV_CVAL_EL0);
SPECIAL_REG_GEN_READ(CPACR_EL1);
SPECIAL_REG_GEN_WRITE(CPACR_EL1);
#define CPACR_FPEN_SHIFT 20
#define CPACR_FPEN_MASK (UWORD64(0x3) << CPACR_FPEN_SHIFT)
#define CPACR_FPEN_TRAP_ALL 0x0
#define CPACR_FPEN_TRAP_NONE 0x3
SPECIAL_REG_GEN_READ(CurrentEL);
#define CURRENT_EL_EL0 0x0
#define CURRENT_EL_EL1 0x4
#define CURRENT_EL_EL2 0x8
#define CURRENT_EL_EL3 0xc
SPECIAL_REG_GEN_READ(DAIF);
SPECIAL_REG_GEN_WRITE(DAIF);
#define DAIF_IRQ_SHIFT 7
#define DAIF_IRQ_FLAG (UWORD64(1) << DAIF_IRQ_SHIFT)
SPECIAL_REG_GEN_WRITE(ELR_EL1);
SPECIAL_REG_GEN_READ(ESR_EL1);
#define ESR_EC_SHIFT 26
#define ESR_EC_MASK (UWORD64(0x3f) << ESR_EC_SHIFT)
#define ESR_EC_FP 0x07
#define ESR_EC_SVC 0x15
#define ESR_EC_IA_LOWER_EL 0x20
#define ESR_EC_DA_LOWER_EL 0x24
#define ESR_EC_DA_CURRENT_EL 0x25
#define ESR_IDFSC_SHIFT 0
#define ESR_IDFSC_MASK (UWORD64(0x3f) << ESR_IDFSC_SHIFT)
#define ESR_IDA_IDFSC_TF0 0x4
#define ESR_IDA_IDFSC_TF1 0x5
#define ESR_IDA_IDFSC_TF2 0x6
#define ESR_IDA_IDFSC_TF3 0x7
#define ESR_DA_WNR_SHIFT 6
#define ESR_DA_WNR_FLAG (UWORD64(1) << ESR_DA_WNR_SHIFT)
SPECIAL_REG_GEN_READ(FAR_EL1);
SPECIAL_REG_GEN_READ(MIDR_EL1);
#define MIDR_REVISION_SHIFT 0
#define MIDR_REVISION_MASK (UWORD64(0xf) << MIDR_REVISION_SHIFT)
#define MIDR_PARTNUM_SHIFT 4
#define MIDR_PARTNUM_MASK (UWORD64(0xfff) << MIDR_PARTNUM_SHIFT)
#define MIDR_VARIANT_SHIFT 20
#define MIDR_VARIANT_MASK (UWORD64(0xf) << MIDR_VARIANT_SHIFT)
#define MIDR_IMPLEMENTER_SHIFT 24
#define MIDR_IMPLEMENTER_MASK (UWORD64(0xff) << MIDR_IMPLEMENTER_SHIFT)
#define SCTLR_M_SHIFT 0
#define SCTLR_M_FLAG (UWORD64(1) << SCTLR_M_SHIFT)
SPECIAL_REG_GEN_WRITE(SP_EL0);
SPECIAL_REG_GEN_READ(SPSR_EL1);
SPECIAL_REG_GEN_WRITE(SPSR_EL1);
#define SPSR_MODE_SHIFT 0
#define SPSR_MODE_MASK (UWORD64(0x1f) << SPSR_MODE_SHIFT)
#define SPSR_MODE_ARM64_EL0T 0x00
SPECIAL_REG_GEN_WRITE(TPIDR_EL0);
SPECIAL_REG_GEN_WRITE(TTBR0_EL1);
SPECIAL_REG_GEN_WRITE(TTBR1_EL1);
#define TTBR0_ASID_SHIFT 48
SPECIAL_REG_GEN_WRITE(VBAR_EL1);
#define TLBI_ASID_SHIFT 48
#endif
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