HelenOS sources
This source file includes following definitions.
- gicv2_enable_irq
- gicv2_connection
- gicv2_add
- gicv2_remove
- gicv2_gone
#include <async.h>
#include <bitops.h>
#include <ddi.h>
#include <ddf/log.h>
#include <errno.h>
#include <macros.h>
#include <str_error.h>
#include <ipc/irc.h>
#include <stdint.h>
#include "gicv2.h"
typedef struct {
ioport32_t ctlr;
#define GICV2D_CTLR_ENABLE_FLAG 0x1
const ioport32_t typer;
#define GICV2D_TYPER_IT_LINES_NUMBER_SHIFT 0
#define GICV2D_TYPER_IT_LINES_NUMBER_MASK \
(0x1f << GICV2D_TYPER_IT_LINES_NUMBER_SHIFT)
const ioport32_t iidr;
PADD32(5);
ioport32_t impl[8];
PADD32(16);
ioport32_t igroupr[32];
ioport32_t isenabler[32];
ioport32_t icenabler[32];
ioport32_t ispendr[32];
ioport32_t icpendr[32];
ioport32_t isactiver[32];
ioport32_t icactiver[32];
ioport32_t ipriorityr[255];
PADD32(1);
ioport32_t itargetsr[255];
PADD32(1);
ioport32_t icfgr[64];
ioport32_t impl2[64];
ioport32_t nsacr[64];
ioport32_t sgir;
PADD32(3);
ioport32_t cpendsgir[4];
ioport32_t spendsgir[4];
PADD32(40);
const ioport32_t impl3[12];
} gicv2_distr_regs_t;
typedef struct {
ioport32_t ctlr;
#define GICV2C_CTLR_ENABLE_FLAG 0x1
ioport32_t pmr;
ioport32_t bpr;
const ioport32_t iar;
#define GICV2C_IAR_INTERRUPT_ID_SHIFT 0
#define GICV2C_IAR_INTERRUPT_ID_MASK \
(0x3ff << GICV2C_IAR_INTERRUPT_ID_SHIFT)
#define GICV2C_IAR_CPUID_SHIFT 10
#define GICV2C_IAR_CPUID_MASK \
(0x7 << GICV2C_IAR_CPUID_SHIFT)
ioport32_t eoir;
const ioport32_t rpr;
const ioport32_t hppir;
ioport32_t abpr;
const ioport32_t aiar;
ioport32_t aeoir;
const ioport32_t ahppir;
PADD32(5);
ioport32_t impl[36];
ioport32_t apr[4];
ioport32_t nsapr[4];
PADD32(3);
const ioport32_t iidr;
PADD32(960);
ioport32_t dir;
} gicv2_cpui_regs_t;
static errno_t gicv2_enable_irq(gicv2_t *gicv2, sysarg_t irq)
{
if (irq > gicv2->max_irq)
return EINVAL;
ddf_msg(LVL_NOTE, "Enable interrupt '%" PRIun "'.", irq);
gicv2_distr_regs_t *distr = (gicv2_distr_regs_t *) gicv2->distr;
pio_write_32(&distr->isenabler[irq / 32], BIT_V(uint32_t, irq % 32));
return EOK;
}
static void gicv2_connection(ipc_call_t *icall, void *arg)
{
ipc_call_t call;
gicv2_t *gicv2;
async_answer_0(icall, EOK);
gicv2 = (gicv2_t *)ddf_dev_data_get(ddf_fun_get_dev((ddf_fun_t *)arg));
while (true) {
async_get_call(&call);
if (!ipc_get_imethod(&call)) {
async_answer_0(&call, EOK);
return;
}
switch (ipc_get_imethod(&call)) {
case IRC_ENABLE_INTERRUPT:
async_answer_0(&call,
gicv2_enable_irq(gicv2, ipc_get_arg1(&call)));
break;
case IRC_DISABLE_INTERRUPT:
async_answer_0(&call, EOK);
break;
case IRC_CLEAR_INTERRUPT:
async_answer_0(&call, EOK);
break;
default:
async_answer_0(&call, EINVAL);
break;
}
}
}
errno_t gicv2_add(gicv2_t *gicv2, gicv2_res_t *res)
{
ddf_fun_t *fun_a = NULL;
errno_t rc;
rc = pio_enable((void *) res->distr_base, sizeof(gicv2_distr_regs_t),
&gicv2->distr);
if (rc != EOK) {
ddf_msg(
LVL_ERROR, "Error enabling PIO for distributor registers.");
goto error;
}
rc = pio_enable(
(void *) res->cpui_base, sizeof(gicv2_cpui_regs_t), &gicv2->cpui);
if (rc != EOK) {
ddf_msg(LVL_ERROR,
"Error enabling PIO for CPU interface registers.");
goto error;
}
fun_a = ddf_fun_create(gicv2->dev, fun_exposed, "a");
if (fun_a == NULL) {
ddf_msg(LVL_ERROR, "Failed creating function 'a'.");
rc = ENOMEM;
goto error;
}
ddf_fun_set_conn_handler(fun_a, gicv2_connection);
rc = ddf_fun_bind(fun_a);
if (rc != EOK) {
ddf_msg(LVL_ERROR, "Failed binding function 'a': %s",
str_error(rc));
goto error;
}
rc = ddf_fun_add_to_category(fun_a, "irc");
if (rc != EOK)
goto error;
gicv2_distr_regs_t *distr = (gicv2_distr_regs_t *) gicv2->distr;
uint32_t typer = pio_read_32(&distr->typer);
gicv2->max_irq = (((typer & GICV2D_TYPER_IT_LINES_NUMBER_MASK) >>
GICV2D_TYPER_IT_LINES_NUMBER_SHIFT) + 1) * 32;
return EOK;
error:
if (fun_a != NULL)
ddf_fun_destroy(fun_a);
return rc;
}
errno_t gicv2_remove(gicv2_t *gicv2)
{
return ENOTSUP;
}
errno_t gicv2_gone(gicv2_t *gicv2)
{
return ENOTSUP;
}
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