HelenOS sources
This source file includes following definitions.
- ppc32_pre_main
- ppc32_pre_mm_init
- display_register
- ppc32_post_mm_init
- macio_register
- irq_initialize_arch
- ppc32_post_smp_init
- calibrate_delay_loop
- arch_get_initial_sp
- userspace
- arch_construct_function
- arch_reboot
#include <arch.h>
#include <arch/arch.h>
#include <config.h>
#include <arch/boot/boot.h>
#include <genarch/drivers/via-cuda/cuda.h>
#include <genarch/kbrd/kbrd.h>
#include <arch/interrupt.h>
#include <interrupt.h>
#include <genarch/fb/fb.h>
#include <abi/fb/visuals.h>
#include <genarch/ofw/ofw_tree.h>
#include <genarch/ofw/pci.h>
#include <userspace.h>
#include <mm/page.h>
#include <mm/km.h>
#include <time/clock.h>
#include <console/console.h>
#include <sysinfo/sysinfo.h>
#include <ddi/irq.h>
#include <arch/drivers/pic.h>
#include <align.h>
#include <macros.h>
#include <str.h>
#define IRQ_COUNT 64
#define IRQ_CUDA 10
static void ppc32_pre_mm_init(void);
static void ppc32_post_mm_init(void);
static void ppc32_post_smp_init(void);
arch_ops_t ppc32_ops = {
.pre_mm_init = ppc32_pre_mm_init,
.post_mm_init = ppc32_post_mm_init,
.post_smp_init = ppc32_post_smp_init,
};
arch_ops_t *arch_ops = &ppc32_ops;
bootinfo_t bootinfo;
static cir_t pic_cir;
static void *pic_cir_arg;
void ppc32_pre_main(bootinfo_t *bootinfo)
{
init.cnt = min3(bootinfo->taskmap.cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS);
size_t i;
for (i = 0; i < init.cnt; i++) {
init.tasks[i].paddr = KA2PA(bootinfo->taskmap.tasks[i].addr);
init.tasks[i].size = bootinfo->taskmap.tasks[i].size;
str_cpy(init.tasks[i].name, CONFIG_TASK_NAME_BUFLEN,
bootinfo->taskmap.tasks[i].name);
}
memmap.total = bootinfo->memmap.total;
memmap.cnt = min(bootinfo->memmap.cnt, MEMMAP_MAX_RECORDS);
for (i = 0; i < memmap.cnt; i++) {
memmap.zones[i].start = bootinfo->memmap.zones[i].start;
memmap.zones[i].size = bootinfo->memmap.zones[i].size;
}
ballocs.base = bootinfo->ballocs.base;
ballocs.size = bootinfo->ballocs.size;
ofw_tree_init(bootinfo->ofw_root);
}
void ppc32_pre_mm_init(void)
{
interrupt_init();
ofw_tree_node_t *cpus_node;
ofw_tree_node_t *cpu_node;
ofw_tree_property_t *freq_prop;
cpus_node = ofw_tree_lookup("/cpus");
if (!cpus_node)
panic("Could not find cpus node.");
cpu_node = cpus_node->child;
if (!cpu_node)
panic("Could not find first cpu.");
freq_prop = ofw_tree_getprop(cpu_node, "timebase-frequency");
if (!freq_prop)
panic("Could not get frequency property.");
uint32_t freq;
freq = *((uint32_t *) freq_prop->value);
decrementer_start(freq / HZ);
}
#ifdef CONFIG_FB
static bool display_register(ofw_tree_node_t *node, void *arg)
{
uintptr_t fb_addr = 0;
uint32_t fb_width = 0;
uint32_t fb_height = 0;
uint32_t fb_scanline = 0;
unsigned int visual = VISUAL_UNKNOWN;
ofw_tree_property_t *prop = ofw_tree_getprop(node, "address");
if ((prop) && (prop->value))
fb_addr = *((uintptr_t *) prop->value);
prop = ofw_tree_getprop(node, "width");
if ((prop) && (prop->value))
fb_width = *((uint32_t *) prop->value);
prop = ofw_tree_getprop(node, "height");
if ((prop) && (prop->value))
fb_height = *((uint32_t *) prop->value);
prop = ofw_tree_getprop(node, "depth");
if ((prop) && (prop->value)) {
uint32_t fb_bpp = *((uint32_t *) prop->value);
switch (fb_bpp) {
case 8:
visual = VISUAL_INDIRECT_8;
break;
case 15:
visual = VISUAL_RGB_5_5_5_BE;
break;
case 16:
visual = VISUAL_RGB_5_6_5_BE;
break;
case 24:
visual = VISUAL_BGR_8_8_8;
break;
case 32:
visual = VISUAL_RGB_0_8_8_8;
break;
default:
visual = VISUAL_UNKNOWN;
}
}
prop = ofw_tree_getprop(node, "linebytes");
if ((prop) && (prop->value))
fb_scanline = *((uint32_t *) prop->value);
if ((fb_addr) && (fb_width > 0) && (fb_height > 0) &&
(fb_scanline > 0) && (visual != VISUAL_UNKNOWN)) {
fb_properties_t fb_prop = {
.addr = fb_addr,
.offset = 0,
.x = fb_width,
.y = fb_height,
.scan = fb_scanline,
.visual = visual,
};
outdev_t *fbdev = fb_init(&fb_prop);
if (fbdev)
stdout_wire(fbdev);
}
return true;
}
#endif
void ppc32_post_mm_init(void)
{
if (config.cpu_active == 1) {
#ifdef CONFIG_FB
ofw_tree_walk_by_device_type("display", display_register, NULL);
#endif
ofw_sysinfo_map();
irq_init(IRQ_COUNT, IRQ_COUNT);
zone_merge_all();
}
}
static bool macio_register(ofw_tree_node_t *node, void *arg)
{
ofw_pci_reg_t *assigned_address = NULL;
ofw_tree_property_t *prop = ofw_tree_getprop(node, "assigned-addresses");
if ((prop) && (prop->value))
assigned_address = ((ofw_pci_reg_t *) prop->value);
if (assigned_address) {
pic_init(assigned_address[0].addr, PAGE_SIZE, &pic_cir,
&pic_cir_arg);
#ifdef CONFIG_MAC_KBD
uintptr_t pa = assigned_address[0].addr + 0x16000;
size_t size = 2 * PAGE_SIZE;
cuda_t *cuda = (cuda_t *) km_map(pa, size, KM_NATURAL_ALIGNMENT,
PAGE_WRITE | PAGE_NOT_CACHEABLE);
cuda_instance_t *cuda_instance =
cuda_init(cuda, IRQ_CUDA, pic_cir, pic_cir_arg);
if (cuda_instance) {
kbrd_instance_t *kbrd_instance = kbrd_init();
if (kbrd_instance) {
indev_t *sink = stdin_wire();
indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
cuda_wire(cuda_instance, kbrd);
pic_enable_interrupt(IRQ_CUDA);
}
}
sysinfo_set_item_val("cuda", NULL, true);
sysinfo_set_item_val("cuda.inr", NULL, IRQ_CUDA);
sysinfo_set_item_val("cuda.address.physical", NULL, pa);
#endif
}
return false;
}
void irq_initialize_arch(irq_t *irq)
{
irq->cir = pic_cir;
irq->cir_arg = pic_cir_arg;
irq->preack = true;
}
void ppc32_post_smp_init(void)
{
static const char *platform = "mac";
sysinfo_set_item_data("platform", NULL, (void *) platform,
str_size(platform));
ofw_tree_walk_by_device_type("mac-io", macio_register, NULL);
}
void calibrate_delay_loop(void)
{
}
uintptr_t arch_get_initial_sp(uintptr_t stack_base, uintptr_t stack_size)
{
return stack_base + stack_size - SP_DELTA;
}
void userspace(uintptr_t pc, uintptr_t sp)
{
userspace_asm(0, sp, pc);
unreachable();
}
void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
{
return addr;
}
void arch_reboot(void)
{
while (true)
;
}
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