HelenOS sources
#include <abi/asmtool.h>
#include <arch/exception.h>
#include <arch/istate_struct.h>
.text
FUNCTION_BEGIN(memcpy_from_uspace)
FUNCTION_BEGIN(memcpy_to_uspace)
cbz x2, 2f
mov x3, x0
1:
ldrb w4, [x1], #1
strb w4, [x3], #1
subs x2, x2, #1
b.ne 1b
2:
ret
FUNCTION_END(memcpy_from_uspace)
FUNCTION_END(memcpy_to_uspace)
FUNCTION_BEGIN(memcpy_from_uspace_failover_address)
FUNCTION_BEGIN(memcpy_to_uspace_failover_address)
mov x0, #0
ret
FUNCTION_END(memcpy_from_uspace_failover_address)
FUNCTION_END(memcpy_to_uspace_failover_address)
FUNCTION_BEGIN(smc_coherence)
mov x9, x0
mov x10, xzr
__dc_loop:
dc cvau, x9
add x9, x9, #4
add x10, x10, #4
cmp x10, x1
blo __dc_loop
dsb ish
mov x9, x0
mov x10, xzr
__ic_loop:
ic ivau, x9
add x9, x9, #4
add x10, x10, #4
cmp x10, x1
blo __ic_loop
dsb ish
isb
ret
FUNCTION_END(smc_coherence)
#if ISTATE_OFFSET_X0 + 8 != ISTATE_OFFSET_X1
#error x0 and x1 are not successive in istate_t
#endif
#if ISTATE_OFFSET_X2 + 8 != ISTATE_OFFSET_X3
#error x2 and x3 are not successive in istate_t
#endif
#if ISTATE_OFFSET_X4 + 8 != ISTATE_OFFSET_X5
#error x4 and x5 are not successive in istate_t
#endif
#if ISTATE_OFFSET_X6 + 8 != ISTATE_OFFSET_X7
#error x6 and x7 are not successive in istate_t
#endif
#if ISTATE_OFFSET_X8 + 8 != ISTATE_OFFSET_X9
#error x8 and x9 are not successive in istate_t
#endif
#if ISTATE_OFFSET_X10 + 8 != ISTATE_OFFSET_X11
#error x10 and x11 are not successive in istate_t
#endif
#if ISTATE_OFFSET_X12 + 8 != ISTATE_OFFSET_X13
#error x12 and x13 are not successive in istate_t
#endif
#if ISTATE_OFFSET_X14 + 8 != ISTATE_OFFSET_X15
#error x14 and x15 are not successive in istate_t
#endif
#if ISTATE_OFFSET_X16 + 8 != ISTATE_OFFSET_X17
#error x16 and x17 are not successive in istate_t
#endif
#if ISTATE_OFFSET_X18 + 8 != ISTATE_OFFSET_X19
#error x18 and x19 are not successive in istate_t
#endif
#if ISTATE_OFFSET_X20 + 8 != ISTATE_OFFSET_X21
#error x20 and x21 are not successive in istate_t
#endif
#if ISTATE_OFFSET_X22 + 8 != ISTATE_OFFSET_X23
#error x22 and x23 are not successive in istate_t
#endif
#if ISTATE_OFFSET_X24 + 8 != ISTATE_OFFSET_X25
#error x24 and x25 are not successive in istate_t
#endif
#if ISTATE_OFFSET_X26 + 8 != ISTATE_OFFSET_X27
#error x26 and x27 are not successive in istate_t
#endif
#if ISTATE_OFFSET_X28 + 8 != ISTATE_OFFSET_X29
#error x28 and x29 are not successive in istate_t
#endif
#if ISTATE_OFFSET_SPSR + 8 != ISTATE_OFFSET_SP
#error spsr and sp are not successive in istate_t
#endif
#if ISTATE_OFFSET_PC + 8 != ISTATE_OFFSET_TPIDR
#error pc and tpidr are not successive in istate_t
#endif
.macro handler i
handler_\i:
sub sp, sp, #ISTATE_SIZE
stp x0, x1, [sp, #ISTATE_OFFSET_X0]
stp x2, x3, [sp, #ISTATE_OFFSET_X2]
stp x4, x5, [sp, #ISTATE_OFFSET_X4]
stp x6, x7, [sp, #ISTATE_OFFSET_X6]
stp x8, x9, [sp, #ISTATE_OFFSET_X8]
stp x10, x11, [sp, #ISTATE_OFFSET_X10]
stp x12, x13, [sp, #ISTATE_OFFSET_X12]
stp x14, x15, [sp, #ISTATE_OFFSET_X14]
stp x16, x17, [sp, #ISTATE_OFFSET_X16]
stp x18, x19, [sp, #ISTATE_OFFSET_X18]
stp x20, x21, [sp, #ISTATE_OFFSET_X20]
stp x22, x23, [sp, #ISTATE_OFFSET_X22]
stp x24, x25, [sp, #ISTATE_OFFSET_X24]
stp x26, x27, [sp, #ISTATE_OFFSET_X26]
stp x28, x29, [sp, #ISTATE_OFFSET_X28]
str x30, [sp, #ISTATE_OFFSET_X30]
mrs x0, spsr_el1
mrs x1, sp_el0
stp x0, x1, [sp, #ISTATE_OFFSET_SPSR]
mrs x0, elr_el1
mrs x1, tpidr_el0
stp x0, x1, [sp, #ISTATE_OFFSET_PC]
mov x0, #\i
mov x1, sp
bl exc_dispatch
ldp x0, x1, [sp, #ISTATE_OFFSET_SPSR]
msr spsr_el1, x0
msr sp_el0, x1
ldp x0, x1, [sp, #ISTATE_OFFSET_PC]
msr elr_el1, x0
b exc_restore_end
.endm
exc_restore_end:
msr tpidr_el0, x1
ldp x0, x1, [sp, #ISTATE_OFFSET_X0]
ldp x2, x3, [sp, #ISTATE_OFFSET_X2]
ldp x4, x5, [sp, #ISTATE_OFFSET_X4]
ldp x6, x7, [sp, #ISTATE_OFFSET_X6]
ldp x8, x9, [sp, #ISTATE_OFFSET_X8]
ldp x10, x11, [sp, #ISTATE_OFFSET_X10]
ldp x12, x13, [sp, #ISTATE_OFFSET_X12]
ldp x14, x15, [sp, #ISTATE_OFFSET_X14]
ldp x16, x17, [sp, #ISTATE_OFFSET_X16]
ldp x18, x19, [sp, #ISTATE_OFFSET_X18]
ldp x20, x21, [sp, #ISTATE_OFFSET_X20]
ldp x22, x23, [sp, #ISTATE_OFFSET_X22]
ldp x24, x25, [sp, #ISTATE_OFFSET_X24]
ldp x26, x27, [sp, #ISTATE_OFFSET_X26]
ldp x28, x29, [sp, #ISTATE_OFFSET_X28]
ldr x30, [sp, #ISTATE_OFFSET_X30]
add sp, sp, #ISTATE_SIZE
eret
.align 11
SYMBOL(exc_vector)
.org exc_vector + 0x000
handler EXC_CURRENT_EL_SP_SEL0_SYNCH
.org exc_vector + 0x080
handler EXC_CURRENT_EL_SP_SEL0_IRQ
.org exc_vector + 0x100
handler EXC_CURRENT_EL_SP_SEL0_FIQ
.org exc_vector + 0x180
handler EXC_CURRENT_EL_SP_SEL0_SERROR
.org exc_vector + 0x200
handler EXC_CURRENT_EL_SP_SELX_SYNCH
.org exc_vector + 0x280
handler EXC_CURRENT_EL_SP_SELX_IRQ
.org exc_vector + 0x300
handler EXC_CURRENT_EL_SP_SELX_FIQ
.org exc_vector + 0x380
handler EXC_CURRENT_EL_SP_SELX_SERROR
.org exc_vector + 0x400
handler EXC_LOWER_EL_AARCH64_SYNCH
.org exc_vector + 0x480
handler EXC_LOWER_EL_AARCH64_IRQ
.org exc_vector + 0x500
handler EXC_LOWER_EL_AARCH64_FIQ
.org exc_vector + 0x580
handler EXC_LOWER_EL_AARCH64_SERROR
.org exc_vector + 0x600
handler EXC_LOWER_EL_AARCH32_SYNCH
.org exc_vector + 0x680
handler EXC_LOWER_EL_AARCH32_IRQ
.org exc_vector + 0x700
handler EXC_LOWER_EL_AARCH32_FIQ
.org exc_vector + 0x780
handler EXC_LOWER_EL_AARCH32_SERROR
.org exc_vector + 0x800
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